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CXB1565R
622Mbps Clock & Data Recovery with High Sensitivity Limitting Amplifier
Description The CXB1565R achieves 3R optical-fiber communication receiver functions (Reshaping and Regenerating and Retiming) on a single chip. This IC also equipped with the signal interruption alarm output, which is used to discriminate the existence of data input. Features * Auto-offset canceler circuit * Signal interruption alarm output * No reference clock required * Single 5V power supply Applications * SONET/SDH: 622.08Mbps * ATM: 622.08Mbps Absolute Maximum Ratings * Supply voltage * Storage temperature * Input voltage difference: | VD - VDN | * TTL input voltage * Output current (Continuous) (Surge) Recommended Operating Conditions * Supply voltage * Termination voltage (for RCK/RDATA) * Termination voltage (for SDE) * Termination resistance (for RCK/RDATA) * Termination resistance (for SDE) * Operating temperature 64 pin LQFP (Plastic)
VCC - VEE Tstg Vdif VinT IO
-0.3 to +7.0 -65 to +150 0 to 2.5 -0.5 to 5.5 0 to 50 0 to 100
V C V V mA mA
VCC - VEE VCC - VT1 VT2 RT1 RT2 Ta
4.5 to 5.5 1.8 to 2.2 VEE 46 to 56 460 to 560 -40 to +85
V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E97323-PS
CXB1565R
Block Diagram and Pin Configuration
CAP1B VEEP1 VEEP1 VEEP2 CAP1
34
LPFB
LPFA
VCCP
VCCP
NC
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
33
VEER1
32 NC 31 VEER2 30 VEER2 29 DN 28 D 27 VCCR1 26 VCCR2 25 DOWN 24 HYS 23 VEER3 22 CAP2 21 CAP3 20 NC 19 NC 18 NC 17 NC 16
NC 49 REXT 50 LKDT 51 VEEG 52 VEEG 53 VCCG 54 EXCK 55 NC 56 CKSEL 57 SQLCH 58 SDC 59 SDE 60 SDEN 61 NC 62 NC 63 NC 64 peak hold peak hold 1 0 Mux. D-FF D CK Reset VCO charge pump Up Down phase/ frequency detector
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VEEE1
VEEG
VEEG
VCCG
VCCG
NC
VCCE1
VEEE2
VCCE1
RCKN
RDATA
RCK
RDATAN
VCCE2
-2-
VCCE2
NC
CXB1565R
Pin Description Typical pin voltage (V) Pin No. Symbol DC AC 1, 16 to 20 2, 3 NC VCCE1 5
VCCE1
Equivalent circuit
Description
No connect Positive supply for RDATA/RDATAN output circuits. 3.3 to 4.1
4
4
RDATA
Retimed data outputs.
5
RDATAN
3.3 to 4.1
5
VEEE1
6 7, 8 52, 53 9, 10 54 11
VEEE1 VEEG VCCG VEEE2
0 0 5 0
VCCE2
Ground for RDATA/RDATAN output circuits. Ground for digital circuits. Positive supply for digital circuits. Ground for RCK/RCKN outputs circuits. 3.3 to 4.1
12
RCKN
12
Recovered clock outputs.
13
RCK
3.3 to 4.1
13
VEEE2
14, 15
VCCE2
5
21 10p 22 VCCR2
Positive supply for RCK/RCKN output circuits.
21
CAP3
3.2 Connect a peak hold capacitor for signal detector. Typically 470pF.
22
CAP2
3.2
5A
5A
VEER3
-3-
CXB1565R
Typical pin voltage (V) Pin No. Symbol DC AC 23 VEER3 0
Equivalent circuit
Description Ground for signal detector.
VCCR2
Bias Generator
24
HYS
0.3
24
VEER3 VCCR2
Connect to VEER3 through a external resistor determine signal detect hysteresis width (P). When connect to VEER3 directly. P 6dB (Typ.) When 8.2k is inserted. P 3dB (Typ.)
25
DOWN
4.4
25
Connect to VCCR2 through a external resistor to decrease signal detect level (SDL). When open, SDL sets to 20mVp-p. (single-ended)
VEER3
26 27 28
VCCR2 VCCR1 D
5 0
Positive supply for signal detector. Positive supply for post amplifier.
VCCR1
Serial data stream inputs. 29 DN
28 29 34 35
34
CAP1
3.7
35 30, 31 32, 36 33 37, 38
CAP1B 3.7 VEER2 NC VEER1 VCCP 0 5 0
VEER1
VEER2
Connect a external capacitor, which determines low cut-off frequency for feedback block. Typically 0.022F.
Ground for post amplifier. No connect Ground for post amplifier. Both VEER1 and VEER2 must be grounded. Positive supply for PLL circuits.
-4-
CXB1565R
Typical pin voltage (V) Pin No. Symbol DC AC
Equivalent circuit
Description
VCCP
39
LPFA
39 40
Connect a external loop filter capacitor. Typically 0.33F.
40
LPFB
VEEP2 VEEP1
41
VEEP2
0
Ground for PLL circuits. No connect Ground for PLL circuits. Both VEEP1 and VEEP2 must be grounded.
VCCP Bias Generator 50 VEEP2
42 to 45 48, 49 NC 56 46, 47 VEEP1 0
50
REXT
0.6
Connect to VEEP1 through a external resistor to determine VCO frequency. Typically 2.4k.
VCCG
51
LKDT
0.2 to 4.8
51
Lock detector (TTL). Driven low, while synchronization is lost. If SQLCH is asserted(low),fixed high even when lock is lost.
VEEG
-5-
CXB1565R
Typical pin voltage (V) Pin No. Symbol DC AC
Equivalent circuit
Description
VCCG
55
EXCK
3
55
External clock input (ECL). For testing only. Normally, left open.
VEEG
VCCG
57
CKSEL
5
57
Clock selector (TTL). When low, EXCK is active instead of VCO output. Normally, left open.
VEEG
VCCG
58
SQLCH
5
58
TTL input. When Low, RCK and RDATA fix Low, in case of data loss. When high, RCK outputs VCO free-run frequency, in case of data loss.
VEEG
VCCG
59
SDC
0.2 to 4.8
59
Signal detect output (TTL). Driven low, while input serial data is lost.
VEEG
VCCG
60
SDE Signal detect outputs (ECL). SDE is driven low, while input serial data is lost.
60 61
61
SDEN
VEEG
62 to 64 NC -6-
No connect
CXB1565R
Electrical Characteristics * DC characteristics Item Supply current TTL input High voltage TTL input Low voltage RDATA/RCK output High voltage RDATA/RCK output Low voltage SDE output High voltage SDE output Low voltage TTL output High voltage TTL output Low voltage Maximum input voltage amplitude D/DB input resistance 1 Ta = 0C to +85C Symbol ICC VIHT VILT VOH11 VOL11 VOH21 VOL21 VOHT VOLT Vmax Rin 51 to VCC - 2V 51 to VCC - 2V 510 to VEE 510 to VEE IOH = -0.4mA IOL = 2.1mA 1600 1125 1500 1875 (VCC = +5V 10%, VEE = GND, Ta = -40C to +85C) Conditions All outputs open 2 0 VCC - 1.1 VCC - 1.86 VCC - 1.1 VCC - 1.86 2.6 0.5 Min. Typ. 95 Max. 130 5.5 0.8 VCC - 0.83 VCC - 1.55 VCC - 0.83 VCC - 1.55 Unit mA V V V V V V V V mV
* AC characteristics Item Post amplifier gain Signal detect hysteresis width Signal detect response assert time Symbol GL P Tas
(VCC = +5V 10%, VEE = GND, Ta = -40C to +85C) Conditions Except for output buffer HYS = VEER3, Rd 2k CAP2, CAP3 = 470ps DOWN = OPEN D = 200mVp-p, Single ended 1 1 1 f = 10Hz, 1 3 30Hz, 1 3 300Hz, 1 3 25kHz, 1 3 250kHz, 1 3 1 51 to VCC - 2V, 20% to 80% 51 to VCC - 2V, 20% to 80% 15 15 1.5 1.5 0.15 Min. 40 3 0 2.3 3.6 500 0.1 7.5 100 100 Typ. Max. Unit dB dB s s degrees rms kHz dB
Signal detect response deassert time Tdas RCK/RCKN output jitter PLL band width Jitter peaking RJ fc2
Jitter Tolerance
UI
PLL capture range PLL pull in time RCK/RCKN output rise/fall time Tp TRC/TFC
622.01 622.08 622.15 Mbps 10 250 350 350 500 ms ps ps
RDATA/RDATAN output rise/fall time TRD/TFC
1 D = 50mVp-p (single-ended), 223 - 1 PRBS, under the AC Electrical characteristics measurement circuit. 2 fc: frequency which attenuates the input sinusoidal jitter by 3dB. 3 Bit error rate threshould: 1E - 10
-7-
CXB1565R
DC Electrical Characteristics Measurement Circuit
0.33F
48
47
46
45
44
43
42
41
40
39
38
37
36
35
0.022F
34 33
49 2.4k 50 51 52 53 54 55 56 57 58 59 510 510 60 61 62 63 64 peak hold peak hold 1 0 Mux. D-FF D CK Reset VCO Up charge pump Down phase/ frequency detector
32 31 30 29 28 27 26 25 24 23 470pF 22 21 20 19 18 17 470pF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
51
51
51
51
2V 5V
2V
Vcc
VEE
-8-
CXB1565R
AC Electrical Characteristics Measurement Circuit
5V
33F 0.33F
0.1F 0.022F
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49 50 2.4k 51 52 53 0.1F 54 55 56 57 58 59 510 60 61 510 62 63 64 peak hold peak hold 1 0 Mux. D-FF D CK Reset VCO charge pump Up Down phase/ frequency detector
32 31 30 470pF 50 29 28 27 26 25 24 23 22 470pF 21 470pF 20 19 18 17 470pF 50
1
2 0.1F
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Z = 50
Z = 50
Z = 50
Z = 50
1M
1M
1M
1M
50
50
50
Clock
Data
Clock
Data
Oscilloscope
Oscilloscope
Bit Error Rate Counter
Jitter Source
Pulse Pattern Generator
-9-
Z = 50
0.1F
CXB1565R
Application Circuit
0.33F 48 47 46 45 44 43 42 41 40 39
0.1F
Analog 0.022F Supply 2 37 36 35 34 33
38
49 2.4k 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 peak hold peak hold 1 0 Mux. D-FF D CK Reset VCO Up charge pump Down phase/ frequency detector
32 31 30 29 470pF 28 27 26 Analog 25 Supply1 24 23 470pF 22 470pF 21 20 19 18 17 0.1F 91 91 130 470pF 130
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0.1F
Digital Supply
40H 5V 33F
Digital Supply Analog Supply 1 Analog Supply 2
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 10 -
CXB1565R
Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 29 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1.5k f2: 225kHz C1 (external): 470pF C2 (external): 0.022F R2 (internal): 10k f1: 723Hz
D C1
28 To IC interior 29 C1 R1 R1 R2 34 C2 35 R2
Fig. 1
Feedback frequency response
Amplifier frequency response
Gain
f1
f2 Frequency
Fig. 2
- 11 -
CXB1565R
2. Alarm block This block provides a signal interruption alarm output used for open fibre control (OFC). Signal detect threshold level and hysteresis width are both user adjustable. Signal detect threshold default level is 20mVp-p (single-ended). An external resister Rd between DOWN and VCCR decrease it. Typical characteristics of Rd vs. threshold level is shown in fig. 7, 8. Hysteresis width can be also decreased by an external resister RH. Typical characteristics of RH vs. P is shown in fig. 9. Timing chart of signal detect function is shown in fig. 5. SD response assert/deassert time are decided by peak hold capacitor CR and CS.Their typical value is 470pF each.
VDAS Deassert level VAS Assert level High level
SD output
Low level
Rd
Rh
Cs
CR
Cs : 470pF CR : 470pF 21
Small
VDAS
VAS Large 3dB 3dB Alarm setting input level Hysteresis
26
25
24
23
22
Input electrical signal amplitude
Fig. 3
Fig. 4
Data input (D)
Hysteresis width
Alarm setting level
Alarm output (SDEN)
Alarm output (SDE, SDC) Assert time Deassert time
Fig. 5. Timing Chart
- 12 -
CXB1565R
3. Clock and Data recovery block Clock recovery is reallized by fully integrated phase locked loop (PLL), which needs no external reference clock. PLL accepts scrambled NRZ data with 50% mark density. Two external components Re and Cp are required. Their recommended values are shown in fig. 6.
Cp
47
46
41
40
39
50 Re Re : 2.4k Cp : 0.33F
Fig. 6 Re is a resistor which decides VCO center frequency. To reduce the temperature dependence of the VCO oscillation frequency, Re should have a small temperature coefficient. In addition, Re should place as near as IC terminal to obtain good jitter performance. Cp is a loop filter capacitance. Since loop damping factor is function of Cp, Cp is also important to have a small temperature coefficient. Damping factor is given as 20,000 x Cp (@ = 1/2) 3 Recommended Cp value gives a of 10, and jitter peaking of under 0.1dB is specified.
3 : data transition density
4. Others Pay attention to handling this IC because its electrostatic discharge strength is week.
- 13 -
CXB1565R
Example of Representative Characteristics
Assert/Deassert level [mVp-p, single-ended]
Assert/Deassert level [mVp-p, single-ended]
30 25 20 15 10 5 0 0 5 10 Rd [k] 15 20 Vassert Vdeassert
30 25 20 15 10 5 0 Vassert Vdeassert 0 5 10 Rd [k] 15 20
VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS Rh = 0
VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS Rh = 8.2k
Fig. 7. Rd vs. Assert/Deassert level
Fig. 8. Rd vs. Assert/Deassert level (RH = 8.2k)
30
Vssert/Deassert level [mVp-p, single-ended]
25
20
15
10 Vassert Vdeassert
5
0 0 5000 Rh [] VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS Rd = 10000 15000 20000
Fig. 9. Rh vs. Assert/Deassert level
- 14 -
CXB1565R
400mV/div
500ps/div VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS 50mVp-p single-ended
Fig. 10. RCK/RDATA output waveform
100mV/div
14.6ps (RMS)
50ps/div VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS 50mVp-p single-ended
Fig. 11. RCK output histgram
0 -5 OC-12 mask 100
Amplitude [dB]
Amplitude [UI]
10
-10 -15 -20 -25 101 102 104 103 105 Modulation Frequency [Hz] 106 107
1 OC-12 template
0.1
101
102
104 105 106 103 Modulation Frequency [Hz]
107
VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS 50mVp-p, single-ended
VCC = 5V, Ta = 27C 622.08Mbps, 223 - 1PRBS 50mVp-p, single-ended Threshold = 1E - 10
Fig. 12. Jitter transfer function
Fig. 13. Jitter tolerance
- 15 -
CXB1565R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 0.08 16 + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
- 16 -
0.5 0.2
(11.0)

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